DRAMs having a variety of structures have been previously disclosed; they can be generally divided into stacked capacitor types, trench capacitor types, fin types, and the like. An equivalent circuit such as that used in all types is shown in FIG. 26; the capacitor is formed by means of a insulation film 40 placed between two electrodes 41 and 42, and switch 43 comprises an MOS transistor.
The accumulation charge Q in the capacitor is expressed by the following formula. EQU Q=;CV.sub.dd ( 1)
wherein,
C: capacitance PA1 V.sub.dd : voltage PA1 S: opposing surface area PA1 .epsilon..sub.r : relative dielectric constant PA1 .epsilon..sub.o : dielectric constant of the insulating film PA1 d: insulation film thickness PA1 a first process, in which a substrate and a first region of opposite conductive type are formed, and the surface of the first region of the substrate, the surface of which is covered with an insulation film is exposed, PA1 a second process, in which a metal thin film comprising at least 1 layer is formed, PA1 a third process, in which a thin film comprising an oxide of a metal is formed on the surface of said metal thin film by means of the direct oxidation of the surface of the metal thin film, PA1 a fourth process, in which a conductive thin film having at least 1 layer is formed, and PA1 a fifth process, in which an interlayer insulation film is formed, and thereafter, wiring lines are formed.
Furthermore, C is expressed by means of the following formula. EQU C: S.epsilon..sub.r .epsilon..sub.o /d (2)
Herein,
In the case in which a leak of a more or less fixed size is present in the packaged memory, if such a leak having a fixed size is permitted, it is preferable that accumulation charge Q be as large as possible. In order to increase the size of accumulated charge Q, as is clear from formulas (1) and (2), the size of dielectric constant e o may be enlarged, the opposing surface area S may be increased, or the insulation film thickness d may be reduced.
However, the recent increase in the density of DRAMs has been striking, enterring the submicron realm. When such an increase in density is carried out, the value of the opposing surface area S is reduced, and when the value of S is reduced, as can be seen from the above formulas, the capacitance C is also reduced. As a result, various methods have been attempted to increase the value of C by increasing the value of .epsilon..sub.o or of S.
However, an increase in the dielectric constant would appear from formulas (1) and (2) to lead to an increase in the accumulation charge Q; however, materials having a large dielectric constant .epsilon..sub.o have poor insulating properties, and as a result, the likelihood of charge leaks increases. An increase in .epsilon..sub.o has been carried out.
Accordingly, in order to increase the accumulation charge Q, it is not sufficient to merely increase the value of capacitance C by increasing the value of .epsilon..sub.o or the value of opposing surface area S, but rather, the insulating characteristics must be improved.
Here, to consider the conventional technology, improvements to the DRAMs having the structures described above have been attempted in order to maintain the capacitance C at a level above a specified value (40 fF or more). The trench capacitance type has the structure shown in FIG. 27, the fin type has the structure shown in FIG. 28, and the stacked capacitor type has the structure shown in FIG. 29.
In the trench capacitor type, an attempt is made to increase the opposing surface area S, and thus the capacitance, by filling a groove with an insulation film 23 and a metal film 12.
However, when the groove in a trench capacitor type becomes deep, and the aspect ratio thereof reaches a level of 20-30, the cleaning of the interior of the groove becomes difficult, and film deposition may be conducted on the contaminated surface. Furthermore, insulation breakdown occurs easily in the corner areas of the groove, so that the reliability and yield thereof are extremely poor.
The fin type is employed in order to increase the opposing surface area by means of the multilayering of metal film 12, and in order to thus increase the capacitance. However, it is also difficult to conduct cleaning in the interior of the very detailed structure of the fin type, and furthermore, defects in resistance to insulation breakdown occur easily at edge areas thereof.
On the other hand, the stacked capacitor type is easier to manufacture than the trench capacitor type or the fin type, and furthermore, has superior reliability and yield.
Conventionally, a stacked capacitor type was produced in the following manner. To explain based on FIGS. 30 and 31, the surface of an N.sup.+ region 7 which was covered by an insulation film 3 was exposed by means of an RIE method (reactive ion etching), or the like, and a conductive film 12 was formed thereon by means of depositting polysilicon; after this, a resist 15 was formed with a desired pattern by means of resist application and photolithography (FIG. 30(a)) and a first electrode 12d was formed by means of RIE (FIG. 30(b)). Next, the surface of a base electrode 2d was oxidized by means of heating in an oxidizing atmosphere, and an insulation film 13 comprising polysilicon oxides was formed on the surface of the lower electrode 12d (FIG. 31(a)); after this, polysilicon was deposited over the entire surface by means of a CVD method, thus forming an upper electrode 14 (FIG. 31(b)). In accordance with this method, the insulation film 13 comprises SiO.sub.2 ; however, as the dielectric constant of SiO.sub.2 is low, having a value of 3.9, it was impossible to obtain an DRAM memory cell having large capacitance.
Attempts have been made to deposit, in the state shown in FIG. 31(b), Si.sub.2 N.sub.3, which has a higher dielectric constant (dielectric constant: 8.0) than that of SiO.sub.2 , to utilize this Si.sub.2 N.sub.3 as an insulation film (FIG. 31(a')), and to deposit polysilicon on top of this to form an upper electrode 14 (FIG. 31(b')). However, as the insulation film is a deposition film, it includes a plurality of pin holes, and accordingly, deficiencies In breakdown resistance occurred easily. Furthermore, attempts were made to close these pin holes by means of heating processing after the deposition of the Si.sub.2 N.sub.3. However, in the course of these attempts, the surface of the Si.sub.2 N.sub.3 was oxidized as a result of the heating processing, and became SiN.sub.x O.sub.y, so that the actual dielectric constant had a value within a range of 3.9-8, and the dielectric constant thus decreased in an undesirable manner as a result of the heating processing.
Thus, a DRAM memory cell having a capacitor with a large capacitance and having a high breakdown voltage was not conventionally available.
It is an object of the present invention to provide a manufacturing method for DRAM memory cells which are easily manufactured, have a high yield, have a high breakdown voltage, and have a large capacitance.